Aim of the course:

The aim of this course is to:
- provide systematic knowledge and skills for developing artificial intelligence chips;
- give an overview about artificial intelligence models and platforms, and to teach how to use the methods and tools necessary for development;
- give an overview of artificial intelligence hardware architectures and chip design, and to teach how to use the methods and tools necessary for development.

Target group:

Company experts, engineers and chip designers who develop or select chips for running AI applications.

Prerequisites:

Bachelor's degree

Topics:

Artificial Intelligence Models and Platforms
1. Matrix multiplication as a central computational core for deep learning (DL) inference/teaching, computational primitives.
2. CNNs, RNNs and transformers, their impact at the operator level.
3. Edge and cloud AI trade-offs (latency, privacy, cost, power consumption, availability).
4. Quantization and pruning techniques to reduce latency, memory usage, and power consumption while maintaining accuracy.
5. Machine learning frameworks and compilers (PyTorch/TensorFlow + ONNX/TFLite/TVM), tools for resource-constrained hardware.

AI hardware architectures and chip design
1. Comparison of processors (CPU), graphics processing units (GPU), artificial intelligence accelerators (TPU), and ASIC accelerators for artificial intelligence workloads.
2. Trade-offs between FPGA and ASIC solutions in accelerating artificial intelligence.
3. Basic concepts of HDL and RTL for creating and analyzing simpler data processing and control logic diagrams.
4. System-on-Chip (SoC) hardware architecture in artificial intelligence chips.
5. Design and evaluation of MAC and systolic arrays, vector/SIMD units, and SIMT implementation.
6. Memory hierarchy, interconnects and dataflow analysis.
7. Main stages of chip design - synthesis, physical implementation.

Study results:

After completing this course the student:
- compares CNNs, RNNs, and transformers and understands their impact at the operator level;
- distinguishes the trade-offs between Edge and Cloud AI (latency, privacy, cost, energy consumption, availability);
- implements quantization and pruning techniques to reduce latency, memory usage, and power consumption while maintaining accuracy;
- compares processors (CPU), graphics processing units (GPU), artificial intelligence accelerators (TPU), and ASIC accelerators for AI workloads;
- explains the trade-offs between FPGA and ASIC solutions for accelerating artificial intelligence;
- describes the hardware architecture of a System-on-Chip (SoC) in artificial intelligence chips and the basic steps of chip design (synthesis, physical implementation).

Graduation document:

TalTech certificate

Language:

English

Lecturer:

Registration deadline:

30.10.2026 23:59

Timetable: