Aim of the course:

The aim of this course is to:
- elaborate knowledge of the design process from design description in SystemVerilog through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming;
- provide experience in designing and verifying digital systems using synthesis and simulation tools;
- provide students the theory and practice of rapid prototyping of digital systems in a laboratory environment;
- develop the ability to combine the knowledge and skills needed for integration of the computer engineering and signal processing;
- to provide students an understanding of specifying, designing and analyzing of asynchronous systems.

Target group:

Company experts, engineers and chip designers who develop or select chips for running AI applications.

Prerequisites:

Bachelor's degree

Topics:

Digital systems design methodology using SystemVerilog and PLD (FPGA). FPGAs as means for building reconfigurable systems. Rapid prototyping of digital systems. Digital signal processing with FPGA devices. Principles of asynchronous design (a systems perspective). The course is based on the development of a real-world projects and case studies.

Study results:

After completing this course the student:
- proceeds from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools;
- understands how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design;
- integrates heterogeneous blocks such as digital hardware and analog interfaces while optimizing power consumption, performance, cost;
- applies hardware design techniques to simulate, synthesize, and test digital signal processing systems;
- understands and comprehends asynchronous design methods, computational models, design terminology.

Graduation document:

TalTech certificate

Language:

English

Lecturer:

Registration deadline:

30.10.2026 23:59

Timetable: