Tallinn University of Technology

Department of Computer Systems

Thesis topics for master's students

With MATLAB/Simulink support package for Arduino (or for Raspberry Pi) develop and test your own control problem algorithm in MATLAB/Simulink and deploy to the controller using automatic code generation; proper hardware selection; interactive algorithm parameters tuning. (https://se.mathworks.com/solutions/embedded-systems.html)

Keywords: Arduino, Matlab, embedded code generation

Supervisor(s):

  • Andres Rähni

Building hardware for work or hobby projects together with programming used controllers.

Keywords: hardware, controllers

Supervisor(s):

  • Peeter Ellervee

Previously achieved results: https://github.com/RedFox20/CraneVR

Keywords: VR, dynamic systems

Supervisor(s):

  • Kristina Vassiljeva
  • Aleksei Tepljakov
  • Eduard Petlenkov

Supervisor(s):

  • Vladimir Viies

Supervisor(s):

  • Kristina Vassiljeva
  • Eduard Petlenkov

The objective of the thesis is to create a functional CPU model on breadboards or FPGAs with an option to monitor all the CPU internal registers in runtime. Whether the chosen hardware platform will be a breadboard based or a FPGA depends on the level of studies.

In addition to monitor CPU internal register in runtime the model must have an option for automated or manual clocking. Some ideas of the result: https://www.youtube.com/watch?v=fCbAafKLqC8 or https://eater.net/6502. If an FPGA based solution is chosen then a soft-core CPU model is required. However, the runtime output mechanisms must be connected with the FPGA core for monitoring.

Keywords: CPU, hardware, breadboard, FPGA

Supervisor(s):

  • Priit Ruberg

Image recognition using deep learning.

Keywords: machine learning, deep learning, AI, machine vision

Supervisor(s):

  • Eduard Petlenkov
  • Aleksei Tepljakov
  • Kristina Vassiljeva

https://www.youtube.com/watch?v=8wLuMxhuLr8

Keywords: VR, virtual laboratory, control systems

Supervisor(s):

  • Aleksei Tepljakov

http://fomcon.net

Keywords: control, modeling, dynamic systems, fractional order systems, fractional calculus

Supervisor(s):

  • Aleksei Tepljakov

Supervisor(s):

  • Kalle Tammemäe

In high-level synthesis, models of different functional units are important library elements. These models are used when selecting type of a unit and when binding operations to hardware modules. In addition, these models should give first the needed information about implementation cost (area, delay, etc.) but these models should be also used in the following synthesis phases, especially at register transfer level synthesis. Generic VHDL models satisfy both requirements but they can be used also for simulation.

Task
To design and validate generic arithmetic modules in VHDL. The modules must satisfy the following criteria:

  1. Abstraction level - synthesizable register transfer level, inner structure describes with logic functions.
  2. Language subset - synthesizable VHDL.
  3. Synthesis tools - Synopsys DV and/or Xilinx Vivado.
  4. Generic parameters - word width in bits plus parameter characterizing inner structure depending on the algorithm to be implemented.

Groups of modules
A group can be implemented partially, depending on the parameterization complexity of modules. The selection below is not final and can be changed Also, the students can propose other algorithms too.

  1. Integer multipliers - signed parallel multiplier, unsigned Booth 2/3/4 multipliers, signed and unsigned Radix 2/4/8/16 sequential multipliers.
  2. Integer dividers - signed and unsigned sequential and parallel dividers.
  3. Floating point modules for different data formats.

Prerequisites

  • Obligatory - knowledge of VHDL.
  • Recommended - IAS0600 "Digital systems design with VHDL" and/or IAS0340 "Digital systems modeling and synthesis" have been completed.

Additional information
Example algorithms - http://www.ecs.umass.edu/ece/koren/arith/simulator/

Keywords: high-level synthesis, arithmetic modules

Supervisor(s):

  • Peeter Ellervee

Hardware based Sudoku solver - implementation on eg FPGA usign eg cellular automata. Design of the user interface is also needed.

Keywords: Sudoku, hardware, user interface

Supervisor(s):

  • Peeter Ellervee

Analysis, modeling and control of laboratory-scale replicas of industrial systems.

See also: http://a-lab.ee/equipment

Keywords: identification, control, dynamic systems

Supervisor(s):

  • Kristina Vassiljeva
  • Aleksei Tepljakov
  • Eduard Petlenkov

Supervisor(s):

  • Vladimir Viies

Study of methods for design of adaptive control systems using computational intelligence methods.

Keywords: computational intelligence, control, adaptivity

Supervisor(s):

  • Eduard Petlenkov

Supervisor(s):

  • Vladimir Viies

Description of the work: Your goal will be to take flow information from underwater measurements and visualize them in a unique way. The tasks you will need to perform include basic signal processing (e.g. converting signals from time to frequency domain) and visualization. The measurement data will be available as ASCII and Matlab binary format, and your job will be to turn the signal data into imagery which can aid fluid dynamics researchers in understanding turbulent flows.

What you will learn: You will gain practical experience in signal processing and data visualization, programming with Matlab.

Why does it matter? Flows in Nature are often very different from those in the laboratory. We are studying how those differences are important to biological organisms, especially fish. Many aquatic animals have developed advanced sensory systems which work in turbulent flows. Turbulence includes fast and slow, big and small vortices, and comparing laboratory and natural flows is cumbersome using standard methods. We want to turn our data into stunning pictures and videos which can help researchers study turbulence in a less technical, but more human way.

Contact: Dr. Jeffrey A. Tuhtan group leader of Environmental Sensing and Intelligence, Centre for Biorobotics: jeffrey.tuhtan@taltech.ee

Supervisor(s):

  • Jeffrey Andrew Tuhtan

Mathematical models of technical and control equipment in Matlab/Simulink and  models simulators on industrial controllers; derivation and parametrisation of model; control algorithms; industrial communication for model behavioural simulation.

Keywords: model, PLC, PAC

Supervisor(s):

  • Andres Rähni

Development of the database of Dynamic Systems: https://a-lab.ee/edu/dsdb

Supervisor(s):

  • Aleksei Tepljakov
  • Juri Belikov

Supervisor(s):

  • Vladimir Viies

Supervisor(s):

  • Vladimir Viies

Applying ISO standardized KNX technology for all applications in home and building control, design with ETS commissioning tool, selection of instrumentation, a comparative analysis of the rivals in the field of IoT.  (https://www.knx.org/knx-en/for-professionals/)

Keywords: smart houses, standardized technology

Supervisor(s):

  • Andres Rähni

Freeware Middleware solutions for Systems and devices integration in Smart Buildings. Comparative analysis of solutions, usability of cloud services, standardization of information, cyber security issues. (e.g. https://se.mathworks.com/hardware-support/thingspeak.html)

Keywords: freeware, middleware, cloud services, oBIX, OPC

Supervisor(s):

  • Andres Rähni

Supervisor(s):

  • Vladimir Viies

Study and implementation of Human-Machine Interfaces for Control Systems.

https://www.inductiveautomation.com/resources/article/what-is-hmi

Supervisor(s):

  • Kristina Vassiljeva
  • Aleksei Tepljakov
  • Eduard Petlenkov

Abstract

Security verification is of paramount importance in the face of hardware attacks such as Spectre and Meltdown. In recent times, the use of fuzzing, a well-established software testing method, has gained significant traction in the realm of CPU security verification.

A critical part of a robust fuzzing process involves the generation of diverse, yet efficient input programs designed to run on the processor. This approach is instrumental in finding security-related vulnerabilities, particularly in corner cases.

Within this project, students will undertake an exploration of various machine learning techniques for the purpose of generating mutants of a seed program. This endeavor aims to enhance the efficiency and cost-effectiveness of processor fuzzing, all while ensuring timely execution.

Prerequisites:

  • Useful courses: Machine learning, Computer architecture (Undergrad & Adv.)
  • Programming: Python, (Verilog, VHDL, System Verilog)

References:

Expected Results:

  • Setting up one of the state-of-the-art open source fuzzer
  • Analyz different methods for instruction mutation and morphing
  • Develop new algorithms for instruction mutation and morphing based on machine learning
  • Simulation, producing results and comparing
  • Generate simulation traces

Supervisor: Tara Ghasempouri, email: tara.ghasempouri@taltech.ee

Co-supervisor: Ali Azarpeyvand, email: ali.azarpeyvand@taltech.ee

Smart user interfaces for VR applications.

Keywords: VR, AR, XR, GUI, UI

Supervisor(s):

  • Aleksei Tepljakov
  • Kristina Vassiljeva
  • Eduard Petlenkov

The hardware synthesis design flow consists of different optimization and transformation algorithms. To select a proper algorithm/method, one must know how they work. The purpose of this group of topics is to visualize the work of some of the algorithms in such manner that the result could be used for teaching as additional materials. The visualization should work on many platforms. For that, two languages have been proposed to be used. However, the other languages can be used too.

Algorithms to be implemented

  1. Graph coloring and/or partitioning with greedy and/or exact methods.
  2. Logic functions minimization algorithms - Quine-McCluskey, etc.
  3. Retiming.
  4. Scheduling algorithms - ASAP, ALAP, FD, Hu, etc.

The list is not final and can be changed. Also, the students can propose other algorithms too.

Prerequisites

  • Knowledge of Java (JavaScript) or Tcl/Tk. Instead of those any other multi platform language for graphical user interfaces can be used.
  • Recommended - IAS0340 "Digital systems modeling and synthesis" has been completed.

Keywords: hardware synthesis, optimization algorithms

Supervisor(s):

  • Peeter Ellervee

Abstract:

In this project, students will embark on a journey to revolutionize computing by designing and implementing a RISC-V 32-bit multicycle pipelined processor System-on-Chip (SoC). Through a comprehensive survey of existing RISC-V cores and an in-depth understanding of RISC-V ISA manuals and toolchains, students will develop the skills necessary to bring this open-source architecture to life. With hands-on experience in FPGA implementation and the integration of FreeRTOS for real-time capabilities, students will pave the way for the future of embedded systems and computing.

Possible tasks (depending on the skills and ambition of the student):

  • Understand RISC-V ISA manuals, including instruction formats and privilege levels.
  • Survey existing RISC-V cores to analyse architecture and performance.
  • Set up the RISC-V toolchain, including compilers and simulators.
  • Implement RISC-V design on FPGA using hardware description languages.
  • Study FreeRTOS and support its integration on the RISC-V core for real-time capabilities.


Prerequisites:

Prerequisites include knowledge of digital logic design, computer architecture, programming (C/C++), hardware description languages (Verilog/SystemVerilog), embedded systems, FPGA programming.

Supervisors:

Prof. Tara Ghasempouri;
PhD candidate: Sharjeel Imtiaz

Contact:

tara.ghasempouri@taltech.ee
sharjeel.imtiaz@taltech.ee

Abstract:

This project aims to integrate an AI accelerator, tailored for Convolutional Neural Network (CNN) tasks such as object detection and image classification, into a RISC-V core architecture. Students will survey existing RISC-V cores suitable for AI accelerators, gain a comprehensive understanding of CNNs and their hardware-friendly implementations using Verilog or SystemVerilog, design and implement the AI accelerator hardware, and integrate it into the RISC-V core architecture. Through benchmarking and real-world application scenarios, students will demonstrate the functionality and performance of the integrated system, gaining invaluable experience in hardware design, deep learning, and system integration.

Possible tasks (depending on the skills and ambition of the student):

  • Research RISC-V cores for AI acceleration, focusing on CNN compatibility and performance.
  • Understand CNN architecture and explore Verilog/SystemVerilog implementations for hardware efficiency.
  • Design and optimize AI accelerator hardware for efficient CNN computations.
  • Integrate AI accelerator with RISC-V core, ensuring compatibility through interface development.
  • Implement the system using FPGA synthesis tools, optimizing resource utilization.
  • Develop test benches and conduct hardware-in-the-loop testing to verify functionality and performance.


Prerequisites:

Prerequisite skills for this project include knowledge of digital logic design, Verilog/SystemVerilog programming, FPGA development, CNN concepts, Python programming with TensorFlow/PyTorch, and hardware/software integration.

Supervisors:

Prof. Tara Ghasempouri; PhD candidate: Sharjeel Imtiaz

Contact:

tara.ghasempouri@taltech.ee
sharjeel.imtiaz@taltech.ee

Abstract:

This project focuses on leveraging hardware-software (HW-SW) codesign techniques to implement efficient Convolutional Neural Network (CNN) accelerators for object detection and image classification tasks on the Ultra96V2 Board. Utilizing the TensilAI library, written in Scala and Verilog, students will explore the integration of custom hardware accelerators with software components to achieve high-performance inference on embedded platforms.

Possible tasks (depending on the skills and ambition of the student):

  • Research CNN architecture, HW-SW codesign, and TensilAI library.
  • Design and optimize Verilog-based CNN accelerators for Ultra96V2.
  • Develop Scala software for hardware interfacing and data processing.
  • Integrate hardware accelerators with software components.
  • Implement object detection and image classification CNN models.
  • Optimize solution for speed, power efficiency, and accuracy.
  • Validate accelerators through extensive benchmarking on Ultra96V2.


Prerequisites:

Prerequisite skills for this project include knowledge of digital logic design, Verilog programming, Scala programming, Python programming (particularly with TensorFlow), CNN concepts, FPGA development, HW-SW codesign principles, and familiarity with the PYNQ framework for FPGA-based embedded systems development.

Supervisors:

Prof. Tara Ghasempouri; PhD candidate: Sharjeel Imtiaz

Contact:

tara.ghasempouri@taltech.ee
sharjeel.imtiaz@taltech.ee

Abstract:

This project focuses on the hardware implementation of Winograd Convolution using SystemVerilog/Verilog for efficient image processing on FPGA. Additionally, the project aims to enhance performance through the integration of application-specific approximation techniques utilizing approximate multipliers and adders. The results will be compared with existing algorithms to evaluate the efficacy of the proposed approach in vision applications.

Possible tasks (depending on the skills and ambition of the student):

  • Research Winograd Convolution and approximation techniques.
  • Design hardware modules in SystemVerilog.
  • Implement and optimize on FPGA.
  • Evaluate performance against existing algorithms.


Prerequisites:

Prerequisite skills for this project include knowledge of digital logic design, FPGA programming, SystemVerilog, python programming image processing algorithms, familiarity with Winograd Convolution, and understanding of hardware approximation techniques such as approximate multipliers and adders.

Supervisors:

Prof. Tara Ghasempouri; PhD candidate: Sharjeel Imtiaz

Contact:

tara.ghasempouri@taltech.ee
sharjeel.imtiaz@taltech.ee

Abstract:

This project aims to address the security vulnerabilities posed by software driven physical and architectural attacks such as Spectre and Meltdown on RISC-V processors through RTL (Register Transfer Level) design. Leveraging SystemVerilog assertions, the project focuses on implementing robust countermeasures to mitigate these attacks and enhance the security of RISC-V processors.

Possible tasks (depending on the skills and ambition of the student):

  • Investigate Spectre and Meltdown vulnerabilities, RISC-V processor architecture, and SystemVerilog assertions.
  • Develop designs to simulate Spectre and Meltdown attacks on RISC-V processors.
  • Create SystemVerilog assertions to detect and mitigate vulnerabilities.
  • Integrate countermeasures into the RTL design and verify effectiveness through simulation (SVA).
  • Assess overhead and impact on processor performance.
  • Prepare a comprehensive report on project findings and insights.


Prerequisites:

Prerequisite skills for this project include knowledge of computer architecture, digital design, RTL design using SystemVerilog, security vulnerabilities, and familiarity with verification methodologies.

Supervisors:

Prof. Tara Ghasempouri; PhD candidate: Sharjeel Imtiaz

Contact:

tara.ghasempouri@taltech.ee
sharjeel.imtiaz@taltech.ee