28 May 2025 at 2:00 PM
Udayan Sunil Patankar, "Area Efficient Design and Implementation of a Novel Divider Circuit Block"

Supervisor: Dr. Ants Koel, Thomas Johann Seebeck Department of Electronics, Tallinn University of Technology, Tallinn, Estonia

Co-supervisor: Dr. Tamás Pardy, Thomas Johann Seebeck Department of Electronics, Tallinn University of Technology, Tallinn, Estonia

Expert reviewer: Prof. Emeritus Toomas Rang, Thomas Johann Seebeck Department of Electronics, Tallinn University of Technology, Tallinn, Estonia

Opponents: 

• Prof. Dr. Serge Dos Santos, Associate Professor (Hab. Dir. Rech.), INSA Centre Val de Loire, Blois Campus Department of Industrial Systems; Inserm U1253 iBraiN- University of Tours, Tours, France
• Prof. Dr. András Poppe, Department of Electron Devices, Budapest University of Technology and Economics (BME), Budapest, Hungary

A robust electronic system must support all essential mathematical operations, as addition, subtraction, multiplication, and division form the vital building blocks of modern theories. Among these, division is a derived operation—akin to how multiplication extends from repeated addition, division can be implemented through successive subtraction or multiplication, combined with specific control logic. In embedded systems, digital systems, integrated circuits, and computer architectures, performance is typically measured by three key parameters: time, area, and power. While many techniques have been developed to enhance the efficiency of division operations, such as digit recurrence and functional iteration, most have focused primarily on improving execution time. Techniques like operand scaling, circuit staging, overlapping, and pipelined execution have shown improvements in speed, but they have not significantly reduced the area required for implementation. With the rise of system-on-chip (SoC) applications and the need for efficient computational blocks in compact environments, there is a growing demand for division circuits with a low area footprint. In such contexts, indirect methods of division are insufficient. A direct, compact implementation is necessary to meet the constraints of emerging and critical applications. Although several performance improvement techniques, including pre-scaling operands, carry-save remainders, array implementations, truncations, cascading, and differential LUTs, have been investigated, they have yet to be fully explored in addressing the research gap for simultaneously utilizing multiple performance improvement techniques with individual input operands. Exploiting this underutilized synergy could pave the way for a novel or hybrid method that balances execution time and area optimization. 
This doctoral dissertation focuses on the design and implementation of a reduced-area divider circuit block that leverages the mathematical relationship between the divisor and the dividend. The proposed approach enhances conversion logic, effectively avoiding rounding errors and overlapping regions in the quotient calculation. The design implementation is evaluated through both regular and pseudo-random sequential input patterns and validated against benchmark results generated through simulations and theoretical modeling. To summarize, the proposed novel USP-Awadhoot divider advances the existing state-of-the-art digit recurrence division by employing multiple performance improvement techniques simultaneously (i.e., dynamic separate scaling operations) on individual input operands. This approach achieves variable latency and a small area footprint while preventing overlapping regions in the quotient calculation logic and offers a highly efficient and compact division solution suited for modern computing systems.

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